From e9fadcd4190e78c38048e70e14ec68bd1d7b4965 Mon Sep 17 00:00:00 2001 From: "J.P. Krauss" Date: Mon, 9 Mar 2026 17:29:28 -0700 Subject: [PATCH] WTF - PCB file missing an embedded frame --- Test_5.kicad_pcb | 31 +++++++++++++++++++++++++++++++ Test_5.kicad_pro | 12 ++++++------ 2 files changed, 37 insertions(+), 6 deletions(-) diff --git a/Test_5.kicad_pcb b/Test_5.kicad_pcb index c180c87..f568940 100644 --- a/Test_5.kicad_pcb +++ b/Test_5.kicad_pcb @@ -38280,4 +38280,35 @@ (members "a5f81d6a-d240-49d4-b391-6a6d4f8c7299" "c1ba8c2d-24bd-4994-a48a-d87e0eb565a3") ) (embedded_fonts no) + (embedded_files + (file + (name "Asymworks_PCB.kicad_wks") + (type worksheet) + (data |KLUv/WAyHT0oAFYxlifgsOgB6B/TaihzMAtjwWvhy0bWQgwDiLqlEGyMyuECICmDGeaDmBeLAIcA + jwBusX23W8z2Cq7I2nLHN7aZTL42GM7PXizN1mR/r2D7zrWPXmltsvrW1s4cx23GwvuyOpP3zhRN + 3pjL1e45vhdtZaptsdiAfM05ZlfuhcUXG5Dtuc242caw++FwAGgqts1cq07l6LxvxVaYxnGdt6Ut + tpeHA2CAvvfgu3ecb6atxcMBkFFcVBXruhSPGnLcXpaFuhb9vdsYliJ4ERMGapISXMIgTdJDNIlv + Pg+VrVZZaWzyyec9fP7vXHP0/eu0+EYIXuZis+hgqy/bv/lcq082qbXeaLuxvXxjuTurmJDvD9q8 + dEehUNyDDwfOlufyPcsa5zm+MeymbOmgfHdyg6EvfLdlNVZri3W+NubOnUNxZYwScgGSRBHpoMCg + oUqYoISKkhAwmZXg+yK4n/FjqxJSRQ7TJLkJeQqipiqaoCgSTSr8Nre1J7eZZTE7+UejCGQw1Vgt + Zl3PjI3GSfRQQSADSeGrxzfpnBFO+BrcCHBL9o0ADYGH9GnQJ9zWYqba6BNJGCQe/AZjpBqkicEU + QZ45/3n81xnLl3QVXmStLYlj1g0AA482CGHdtxK5xVBVvv+fzrXn+cdW/2EGr9jMISJSsBBNE1Sd + +ydBkKaIwtfi+4cvN7M0zuZgxHln/E42GiNtL4pQEgWfFn9fqtJvzz/8Kt8zJ1HBgoOkQoCAPHTt + JW1xYxI1QA1z4nyza2Enj7aUTIXEL/heWBoC5dNmxp0ylsQtdg/o8zT3AoEgoJGtQqhIRgoKkmSY + AwEJMYxQycx6dFqArRcghx9lFQqJzJXp/QgqLbqIGWghWmGbXCG223/WeqINra6qJ0D6idcqg+/0 + Sw7XkhY4ouYAvIw/ubuEJXFTzCETIbaXTtfv+lY7dXpeOtlTKvGTqjljV9NFjNbrwWzpOfNGyMS9 + 2lxYMsnQT0yTIWJF+4Lg1BRoX96rpaxn5xnWHooOjnvZgeRBYuN0vBmXZHTkvjYHxMKFRy7AEap/ + 5FIP8tIysayIhK8kXLX7SknrgJOIJlIMMj6aRDHAf+O+K3eDTsovTQQ+xRh8DQQYM9PXLnr5lx3+ + Q8Qc6r5FW/+YkLhOKuR8kgn+pUTFGIct9E5b+OBnUh6njA0l8oudZwmeJGJekJ+qEFZAUgXsqPuS + 7EuuczrEZQgV5lx41iEaIE+etuAhGWA6RrlXRhJOnCWEU+gE1auEoAf9jF4CIOKiZcBvaL5z62yM + b5Q4VLEM4HwjZyQnSivicHPU8OKBlDMhv1o7ODxgamU8HwX9MF8WjwqC53qsJ/A9fWwCz+0anlia + l8cdoMBw5SmFUFqnQbshmUI7SOt0KIEDnNRbh6J14CEyukNNZ3gSiuP0ib87eXbcwIIgsIdiTbBk + rVCjATEiDbgH0JXABgpoI/vFiXPiBDStxFcn42wPNtMQgAQ6KcgExtVLErQq2s0U6bEFeVsN3SP+ + 5VCSsL/R0eONxTBwnUayBoUv6Wd+MX4jVoPAv3NiK7CJBQgj6TLUfSlEhw2cMjHzd9ariTKQxCeR + P5mg7MdpR14ku/LMMNjsZzJ8loAs8+hQc0S+nYkFAW4EiPOE0VT6lQDuzmc0wqQ9voS9LwqPUTNf + El5kzAK+B7rxUQ7pENg2XQ3lMNVd33G0uGqX2AUyyvEd4nt31SBq40OuAg==| + ) + (checksum "644A6284571AF05FC533C42BDC87F7D2") + ) + ) ) diff --git a/Test_5.kicad_pro b/Test_5.kicad_pro index 2547fd2..9ebf4d6 100644 --- a/Test_5.kicad_pro +++ b/Test_5.kicad_pro @@ -652,7 +652,7 @@ "svg": "", "vrml": "" }, - "page_layout_descr_file": "${KIPRJMOD}/templates/Asymworks_PCB.kicad_wks" + "page_layout_descr_file": "kicad-embed://Asymworks_PCB.kicad_wks" }, "schematic": { "annotate_start_num": 0, @@ -845,9 +845,9 @@ "DWG_TITLE_ASSY": "PCB Assembly, Assembly Name", "DWG_TITLE_PCB": "PCB, Assembly Name", "DWG_TITLE_SCH": "Schematic, Assembly Name", - "FABRICATION_NOTES": "FABRICATION NOTES (UNLESS OTHERWISE SPECIFIED)\n\n1)\tFABRICATE PER IPC-6012A CLASS 2.\n\n2)\tOUTLINE DEFINED IN SEPARATE GERBER FILE WITH\n\t\"Edge_Cuts.GBR\" SUFFIX.\n\n3)\tSEE SEPARATE DRILL FILES WITH \".DRL\" SUFFIX \n\tFOR HOLE LOCATIONS.\n\n\tSELECTED HOLE LOCATIONS SHOWN ON THIS DRAWING \n\tFOR REFERENCE ONLY.\n\n4)\tSURFACE FINISH: HAL SNPB\n\n5)\tSOLDERMASK ON BOTH SIDES OF THE BOARD SHALL \n\tBE LPI, COLOR GREEN.\n\n6)\tSILK SCREEN LEGEND TO BE APPLIED PER LAYER \n\tSTACKUP USING WHITE NON-CONDUCTIVE EPOXY INK.\n\n7)\tALL VIAS ARE TENTED ON BOTH SIDES UNLESS \n\tSOLDERMASK OPENED IN GERBER.\n\n8)\tRESERVED\n\n9)\tPCB MATERIAL REQUIREMENTS:\n\n\tA.\tFLAMMABILITY RATING MUST MEET OR EXCEED \n\t\tUL94V-0 REQUIREMENTS.\n\tB.\tTg 135 C OR EQUIVALENT.\n\n10)\tDESIGN GEOMETRY MINIMUM FEATURE SIZES:\n\n\tBOARD SIZE\t\t\t\t46.000 \u00d7 27.500 mm\n\tBOARD THICKNESS\t\t1.647 mm\n\tTRACE WIDTH\t\t\t0.100 mm\n\tTRACE TO TRACE\t\t0.200 mm\n\tMIN. HOLE (PTH)\t\t\t0.300 mm\n\tMIN. HOLE (NPTH)\t\t2.200 mm\n\tANNULAR RING\t\t\t0.150 mm\n\tCOPPER TO HOLE\t\t0.250 mm\n\tCOPPER TO EDGE\t\t0.500 mm\n\tHOLE TO HOLE\t\t\t0.250 mm\n\n11)\tALL DIMENSIONS ARE IN MILLIMETERS UNLESS OTHERWISE\n\tSPECIFIED.\n\n12)\tFOR REFERENCE ONLY THE STACKUP CORRESPONDS TO JLCPCB\n\tSTACKUP JLC04161H-7628.\n\tFOR REFERENCE ONLY. IMPEDANCE IS THE CONTROLLING PARAMETER\n\tOVER LAYER STACKUP. GERBER DATA MAY NOT BE ALTERED EXCEPT\n\tFOR STANDARD FABRICATION ALLOWANCES.\n\n\tTHE SUPPLIED ARTWORK MAY OR MAY NOT CONTAIN THE SPECIFIED\n\tTRACE GEOMETRIES ON EVERY LAYERS SPECIFIED.", - "GIT_HASH": "3223cc4", - "GIT_HASH_PCB": "17ccbe1", + "FABRICATION_NOTES": "FABRICATION NOTES (UNLESS OTHERWISE SPECIFIED)\n\n1)\tFABRICATE PER IPC-6012A CLASS 2.\n\n2)\tOUTLINE DEFINED IN SEPARATE GERBER FILE WITH\n\t\"Edge_Cuts.GBR\" SUFFIX.\n\n3)\tSEE SEPARATE DRILL FILES WITH \".DRL\" SUFFIX \n\tFOR HOLE LOCATIONS.\n\n\tSELECTED HOLE LOCATIONS SHOWN ON THIS DRAWING \n\tFOR REFERENCE ONLY.\n\n4)\tSURFACE FINISH: HAL SNPB\n\n5)\tSOLDERMASK ON BOTH SIDES OF THE BOARD SHALL \n\tBE LPI, COLOR GREEN.\n\n6)\tSILK SCREEN LEGEND TO BE APPLIED PER LAYER \n\tSTACKUP USING WHITE NON-CONDUCTIVE EPOXY INK.\n\n7)\tALL VIAS ARE TENTED ON BOTH SIDES UNLESS \n\tSOLDERMASK OPENED IN GERBER.\n\n8)\tRESERVED\n\n9)\tPCB MATERIAL REQUIREMENTS:\n\n\tA.\tFLAMMABILITY RATING MUST MEET OR EXCEED \n\t\tUL94V-0 REQUIREMENTS.\n\tB.\tTg 135 C OR EQUIVALENT.\n\n10)\tDESIGN GEOMETRY MINIMUM FEATURE SIZES:\n\n\tBOARD SIZE\t\t\t\t46.000 × 27.500 mm\n\tBOARD THICKNESS\t\t1.647 mm\n\tTRACE WIDTH\t\t\t0.100 mm\n\tTRACE TO TRACE\t\t0.200 mm\n\tMIN. HOLE (PTH)\t\t\t0.300 mm\n\tMIN. HOLE (NPTH)\t\t2.200 mm\n\tANNULAR RING\t\t\t0.150 mm\n\tCOPPER TO HOLE\t\t0.250 mm\n\tCOPPER TO EDGE\t\t0.500 mm\n\tHOLE TO HOLE\t\t\t0.250 mm\n\n11)\tALL DIMENSIONS ARE IN MILLIMETERS UNLESS OTHERWISE\n\tSPECIFIED.\n\n12)\tFOR REFERENCE ONLY THE STACKUP CORRESPONDS TO JLCPCB\n\tSTACKUP JLC04161H-7628.\n\tFOR REFERENCE ONLY. IMPEDANCE IS THE CONTROLLING PARAMETER\n\tOVER LAYER STACKUP. GERBER DATA MAY NOT BE ALTERED EXCEPT\n\tFOR STANDARD FABRICATION ALLOWANCES.\n\n\tTHE SUPPLIED ARTWORK MAY OR MAY NOT CONTAIN THE SPECIFIED\n\tTRACE GEOMETRIES ON EVERY LAYERS SPECIFIED.", + "GIT_HASH": "b8fef39", + "GIT_HASH_PCB": "b8fef39", "GIT_HASH_SCH": "5caa450", "GIT_URL": "/jkrauss/Test_4", "PROJECT_CODE": "P99", @@ -855,7 +855,7 @@ "RELEASE_STATE": "WORKING", "REVISION": "NO_TAG+ (Unreleased)", "SCALE": "2:1", - "SCHEMATIC_NOTES": "Unless otherwise specified, components Values are in ohms, \u00b5F, and \u00b5H.", + "SCHEMATIC_NOTES": "Unless otherwise specified, components Values are in ohms, µF, and µH.", "SHEET_NAME_01": "Cover Page", "SHEET_NAME_02": "Block Diagram", "SHEET_NAME_03": "Project Architecture", @@ -879,4 +879,4 @@ "STATE": "TEMPLATE", "VARIANT": "" } -} \ No newline at end of file +}