From f545a5f2176717e21848e7edf0a82afab59a4a65 Mon Sep 17 00:00:00 2001
From: jkrauss <+jkrauss@users.noreply.github.com>
Date: Fri, 6 Mar 2026 21:25:59 +0000
Subject: [PATCH] [bot]: Update Outputs
---
Test_5-netlist.net | 2 +-
Test_5.kicad_pro | 2 +-
Test_5.xml | 2 +-
html/Test_5-navigate.html | 2 -
html/Test_5-navigate_kiri.html | 2 -
html/Test_5-navigate_mfg.html | 2 -
html/Test_5-navigate_mfg_assembly.html | 2 -
html/Test_5-navigate_mfg_fab.html | 2 -
.../Test_5-navigate_mfg_fab_drill-tables.html | 2 -
html/Test_5-navigate_mfg_fab_gerbers.html | 2 -
html/Test_5-navigate_mfg_jlcpcb.html | 2 -
html/Test_5-navigate_mfg_jlcpcb_gerbers.html | 2 -
html/Test_5-navigate_models.html | 2 -
html/Test_5-navigate_panels.html | 2 -
html/Test_5-navigate_panels_panel-800.html | 2 -
html/Test_5-navigate_renders.html | 40 +-
html/Test_5-navigate_reports.html | 2 -
html/Test_5-navigate_schematic.html | 2 -
html/Test_5-navigate_test.html | 2 -
html/Test_5-navigate_test_testpoints.html | 2 -
...bottom_Test_5-blender_3d_angled_bottom.png | Bin 161798 -> 161799 bytes
...ngled_top_Test_5-blender_3d_angled_top.png | Bin 162030 -> 162031 bytes
.../images/cat_panel_801_Test_5-panel_801.png | Bin 89335 -> 89335 bytes
...t_pcbdraw_bottom_Test_5-pcbdraw_bottom.png | Bin 63469 -> 63469 bytes
.../cat_pcbdraw_top_Test_5-pcbdraw_top.png | Bin 70889 -> 70889 bytes
.../cat_pdf_assembly_Test_5-assembly.png | Bin 35787 -> 35787 bytes
.../cat_pdf_drill_map_Test_5--npth_map.png | Bin 16706 -> 16706 bytes
.../cat_pdf_drill_map_Test_5--pth_map.png | Bin 29100 -> 29100 bytes
...cat_pdf_fabrication_Test_5-fabrication.png | Bin 140451 -> 140451 bytes
.../cat_pdf_schematic_Test_5-schematic.png | Bin 94835 -> 94835 bytes
...wer_angled_bottom_Test_5-angled_bottom.png | Bin 124969 -> 88013 bytes
...3d_viewer_angled_top_Test_5-angled_top.png | Bin 144418 -> 128375 bytes
...cat_png_3d_viewer_bottom_Test_5-bottom.png | Bin 114926 -> 66982 bytes
.../cat_png_3d_viewer_top_Test_5-top.png | Bin 120368 -> 89549 bytes
mfg/assembly/Test_5-ibom.html | 2 +-
mfg/fab/Test_5-GERBERS.zip | Bin 1362019 -> 1362019 bytes
mfg/fab/gerbers/Test_5--npth.drl | 4 +-
mfg/fab/gerbers/Test_5--npth_map.pdf | Bin 7415 -> 7415 bytes
mfg/fab/gerbers/Test_5--pth.drl | 4 +-
mfg/fab/gerbers/Test_5--pth_map.pdf | Bin 11147 -> 11147 bytes
mfg/jlcpcb/Test_5-Fabpack.zip | Bin 72629 -> 72628 bytes
mfg/jlcpcb/gerbers/Test_5-B_Cu.gbl | 4 +-
mfg/jlcpcb/gerbers/Test_5-B_Mask.gbs | 4 +-
mfg/jlcpcb/gerbers/Test_5-B_Paste.gbp | 4 +-
mfg/jlcpcb/gerbers/Test_5-B_Silkscreen.gbo | 4 +-
mfg/jlcpcb/gerbers/Test_5-Edge_Cuts.gm1 | 4 +-
mfg/jlcpcb/gerbers/Test_5-F_Cu.gtl | 4 +-
mfg/jlcpcb/gerbers/Test_5-F_Mask.gts | 4 +-
mfg/jlcpcb/gerbers/Test_5-F_Paste.gtp | 4 +-
mfg/jlcpcb/gerbers/Test_5-F_Silkscreen.gto | 4 +-
mfg/jlcpcb/gerbers/Test_5-In1_Cu.g1 | 4 +-
mfg/jlcpcb/gerbers/Test_5-In2_Cu.g2 | 4 +-
models/Test_5-glb.glb | Bin 1464464 -> 1464464 bytes
models/Test_5-step.step | 18172 ++++++++--------
panels/panel-800/Test_5-panel_801.kicad_pro | 1048 +-
panels/panel-800/Test_5-panel_801.png | Bin 187210 -> 187250 bytes
renders/Test_5-angled_bottom.png | Bin 973627 -> 132152 bytes
renders/Test_5-angled_top.png | Bin 1113977 -> 208330 bytes
renders/Test_5-blender_3d_angled_bottom.png | Bin 1354410 -> 1354409 bytes
renders/Test_5-blender_3d_angled_top.png | Bin 1079015 -> 1079003 bytes
...ender_exportblender_3d_angled_bottom.pcb3d | Bin 841521 -> 841521 bytes
...-blender_exportblender_3d_angled_top.pcb3d | Bin 841520 -> 841519 bytes
renders/Test_5-bottom.png | Bin 944161 -> 81945 bytes
renders/Test_5-top.png | Bin 917222 -> 104839 bytes
schematic/Test_5-schematic.pdf | Bin 1731368 -> 1731368 bytes
65 files changed, 9642 insertions(+), 9710 deletions(-)
diff --git a/Test_5-netlist.net b/Test_5-netlist.net
index 38942f7..8f5c370 100644
--- a/Test_5-netlist.net
+++ b/Test_5-netlist.net
@@ -15,7 +15,7 @@
(textvar (name "DWG_TITLE_PCB") "PCB, Assembly Name")
(textvar (name "DWG_TITLE_SCH") "Schematic, Assembly Name")
(textvar (name "FABRICATION_NOTES") "FABRICATION NOTES (UNLESS OTHERWISE SPECIFIED)\n\n1) FABRICATE PER IPC-6012A CLASS 2.\n\n2) OUTLINE DEFINED IN SEPARATE GERBER FILE WITH\n \"Edge_Cuts.GBR\" SUFFIX.\n\n3) SEE SEPARATE DRILL FILES WITH \".DRL\" SUFFIX \n FOR HOLE LOCATIONS.\n\n SELECTED HOLE LOCATIONS SHOWN ON THIS DRAWING \n FOR REFERENCE ONLY.\n\n4) SURFACE FINISH: HAL SNPB\n\n5) SOLDERMASK ON BOTH SIDES OF THE BOARD SHALL \n BE LPI, COLOR GREEN.\n\n6) SILK SCREEN LEGEND TO BE APPLIED PER LAYER \n STACKUP USING WHITE NON-CONDUCTIVE EPOXY INK.\n\n7) ALL VIAS ARE TENTED ON BOTH SIDES UNLESS \n SOLDERMASK OPENED IN GERBER.\n\n8) RESERVED\n\n9) PCB MATERIAL REQUIREMENTS:\n\n A. FLAMMABILITY RATING MUST MEET OR EXCEED \n UL94V-0 REQUIREMENTS.\n B. Tg 135 C OR EQUIVALENT.\n\n10) DESIGN GEOMETRY MINIMUM FEATURE SIZES:\n\n BOARD SIZE 46.000 × 27.500 mm\n BOARD THICKNESS 1.647 mm\n TRACE WIDTH 0.100 mm\n TRACE TO TRACE 0.200 mm\n MIN. HOLE (PTH) 0.300 mm\n MIN. HOLE (NPTH) 2.200 mm\n ANNULAR RING 0.150 mm\n COPPER TO HOLE 0.250 mm\n COPPER TO EDGE 0.500 mm\n HOLE TO HOLE 0.250 mm\n\n11) ALL DIMENSIONS ARE IN MILLIMETERS UNLESS OTHERWISE\n SPECIFIED.")
- (textvar (name "GIT_HASH") "5caa450")
+ (textvar (name "GIT_HASH") "71e6913")
(textvar (name "GIT_HASH_PCB") "4c0c812")
(textvar (name "GIT_HASH_SCH") "5caa450")
(textvar (name "GIT_URL") "/jkrauss/Test_4")
diff --git a/Test_5.kicad_pro b/Test_5.kicad_pro
index b7a9bc9..6f84ef8 100644
--- a/Test_5.kicad_pro
+++ b/Test_5.kicad_pro
@@ -846,7 +846,7 @@
"DWG_TITLE_PCB": "PCB, Assembly Name",
"DWG_TITLE_SCH": "Schematic, Assembly Name",
"FABRICATION_NOTES": "FABRICATION NOTES (UNLESS OTHERWISE SPECIFIED)\n\n1)\tFABRICATE PER IPC-6012A CLASS 2.\n\n2)\tOUTLINE DEFINED IN SEPARATE GERBER FILE WITH\n\t\"Edge_Cuts.GBR\" SUFFIX.\n\n3)\tSEE SEPARATE DRILL FILES WITH \".DRL\" SUFFIX \n\tFOR HOLE LOCATIONS.\n\n\tSELECTED HOLE LOCATIONS SHOWN ON THIS DRAWING \n\tFOR REFERENCE ONLY.\n\n4)\tSURFACE FINISH: HAL SNPB\n\n5)\tSOLDERMASK ON BOTH SIDES OF THE BOARD SHALL \n\tBE LPI, COLOR GREEN.\n\n6)\tSILK SCREEN LEGEND TO BE APPLIED PER LAYER \n\tSTACKUP USING WHITE NON-CONDUCTIVE EPOXY INK.\n\n7)\tALL VIAS ARE TENTED ON BOTH SIDES UNLESS \n\tSOLDERMASK OPENED IN GERBER.\n\n8)\tRESERVED\n\n9)\tPCB MATERIAL REQUIREMENTS:\n\n\tA.\tFLAMMABILITY RATING MUST MEET OR EXCEED \n\t\tUL94V-0 REQUIREMENTS.\n\tB.\tTg 135 C OR EQUIVALENT.\n\n10)\tDESIGN GEOMETRY MINIMUM FEATURE SIZES:\n\n\tBOARD SIZE\t\t\t\t46.000 \u00d7 27.500 mm\n\tBOARD THICKNESS\t\t1.647 mm\n\tTRACE WIDTH\t\t\t0.100 mm\n\tTRACE TO TRACE\t\t0.200 mm\n\tMIN. HOLE (PTH)\t\t\t0.300 mm\n\tMIN. HOLE (NPTH)\t\t2.200 mm\n\tANNULAR RING\t\t\t0.150 mm\n\tCOPPER TO HOLE\t\t0.250 mm\n\tCOPPER TO EDGE\t\t0.500 mm\n\tHOLE TO HOLE\t\t\t0.250 mm\n\n11)\tALL DIMENSIONS ARE IN MILLIMETERS UNLESS OTHERWISE\n\tSPECIFIED.",
- "GIT_HASH": "71e6913",
+ "GIT_HASH": "832f727",
"GIT_HASH_PCB": "4c0c812",
"GIT_HASH_SCH": "5caa450",
"GIT_URL": "/jkrauss/Test_4",
diff --git a/Test_5.xml b/Test_5.xml
index 0b5a6ca..442b09e 100644
--- a/Test_5.xml
+++ b/Test_5.xml
@@ -62,7 +62,7 @@
11) ALL DIMENSIONS ARE IN MILLIMETERS UNLESS OTHERWISE
SPECIFIED.
-
+
Test_5-top.png
png_3d_viewer_top
+
Test_5-bottom.png
png_3d_viewer_bottom
- Test_5-blender_exportblender_3d_top.pcb3d
-blender_3d_top
-
- Test_5-blender_3d_top.png
-blender_3d_top
-
- Test_5-blender_exportblender_3d_bottom.pcb3d
-blender_3d_bottom
-
- Test_5-blender_3d_bottom.png
-blender_3d_bottom
-z$e=z `gsHqG_Q)RHOBZy8~Z7xTU*yd3J=%zt`9Vy
z9nGxt568ZpQb^#}p%B{pM#31w=I-4OJ^RA6oxbsc=~e@rBfv!l*A>bOd##@)
zjhs#nOiuf0Z)TP^)%R>{Uf}y6jxQ&eM)_RtmV>=qr`M7hHVIw|zPe>k)~%+c^UD7P
ze;I~O5Q4@n&Bv-eO#)HuO@q#n{=1M#d&MG!IXzp=3P?Mo_vm3@1uK7&iQ$oH^l=IA
zFTD^*6!*W9P7S=Q@oFYK?qbUGN=7l7Ig3Du!5S-MR4
D}G!vM5rD%I`PE
zG;I)I?L;UmwJeK8Q