diff --git a/.gitattributes b/.gitattributes
new file mode 100644
index 0000000..5282280
--- /dev/null
+++ b/.gitattributes
@@ -0,0 +1,7 @@
+*.csv filter=bom_csv
+*.html filter=bom_html
+*.gbr filter=gerber
+*.gbrjob filter=gbrjob
+*.xml filter=xml
+*.kicad_pcb filter=kicad_pcb_f
+*.net filter=net_filter
diff --git a/.gitconfig b/.gitconfig
new file mode 100644
index 0000000..1238a5e
--- /dev/null
+++ b/.gitconfig
@@ -0,0 +1,20 @@
+[filter "bom_csv"]
+ clean = sed -E 's/^BoM Date:.*$/BoM Date:Date/'
+ smudge = sed -E \"s/BoM Date:Date/BoM Date:,`date +\\\"%a %d %b %Y %X %:::z\\\"`/\"
+[filter "bom_html"]
+ clean = sed -E 's/^
BoM Date<\\/td> `date +\\\"%a %d %b %Y %X %:::z\\\"`<\\/td><\\/tr>/\"
+[filter "gerber"]
+ clean = sed -E -e 's/^%TF.CreationDate,.*$/%TF.CreationDate,Date%/' -e 's/^G04 Created by KiCad.*$/G04 Created by KiCad*/'
+ smudge = sed -E \"s/%TF.CreationDate,Date%/%TF.CreationDate,`date +%Y-%m-%dT%H:%M:%S%:z`/\"
+[filter "gbrjob"]
+ clean = sed -E 's/\"CreationDate\":.*/\"CreationDate\": \"Date\"/'
+ smudge = sed -E \"s/\\\"CreationDate\\\": \\\"Date\\\"/\\\"CreationDate\\\": \\\"`date +%Y-%m-%dT%H:%M:%S%:z`\\\"/\"
+[filter "xml"]
+ clean = sed -E -e 's/^ .*<\\/date>/ Date2<\\/date>/' -e 's/^ .*<\\/date>/ Date1<\\/date>/'
+ smudge = sed -E -e \"s/Date1<\\/date>/`date +\\\"%a %d %b %Y %X %:::z\\\"`<\\/date>/\" -e \"s/Date2<\\/date>/`date +\\\"%Y-%m-%d\\\"`<\\/date>/\"
+[filter "kicad_pcb_f"]
+ clean = sed -E 's/\\(host pcbnew ([[:digit:]]+\\.[[:digit:]]+\\.[[:digit:]]+).*/\\(host pcbnew \\1\\)/'
+[filter "net_filter"]
+ clean = sed -E -e 's/\\(date \\\".*\\\"\\)/\\(date \\\"Date\\\"\\)/'
+ smudge = sed -E -e \"s/\\(date \\\"Date\\\"\\)/\\(date \\\"`date +\\\"%a %d %b %Y %X %:::z\\\"`\\\"\\)/\"
diff --git a/Asymworks_Template-netlist.net b/Asymworks_Template-netlist.net
new file mode 100644
index 0000000..143e547
--- /dev/null
+++ b/Asymworks_Template-netlist.net
@@ -0,0 +1,149 @@
+(export (version "E")
+ (design
+ (source "/workspace/jkrauss/Test_7/Asymworks_Template.kicad_sch")
+ (date "Date")
+ (tool "Eeschema 9.0.7+1")
+ (textvar (name "ASSEMBLY_NAME") "Assembly Name")
+ (textvar (name "ASSEMBLY_NOTES") "ASSEMBLY NOTES (UNLESS OTHERWISE SPECIFIED)\n\n1) DO NOT POPULATE COMPONENTS ARE MARKED WITH A RED CROSS\n\n2) DO NOT POPULATE COMPONENTS ARE NOT PRESENT IN THE BOM\n\n3) IF CONFLICTING INFORMATION IS FOUND BETWEEN THE ASSEMBLY\n FILE AND BOM, BOM SHOULD BE USED AS THE MAIN SOURCE.\n\n4) DOT IDENTIFIES PIN #1 LOCATION AND DEVICE ORIENTATION\n WHEN VIEWED FROM THE TOP.")
+ (textvar (name "ASSEMBLY_NUMBER") "A99-9000")
+ (textvar (name "ASSEMBLY_SCALE") "1")
+ (textvar (name "COMPANY") "Asymworks, LLC")
+ (textvar (name "DESIGNER") "JPK")
+ (textvar (name "DWG_NUMBER_PCB") "P99-9000")
+ (textvar (name "DWG_NUMBER_SCH") "S99-9000")
+ (textvar (name "DWG_TITLE_ASSY") "PCB Assembly, Assembly Name")
+ (textvar (name "DWG_TITLE_PCB") "PCB, Assembly Name")
+ (textvar (name "DWG_TITLE_SCH") "Schematic, Assembly Name")
+ (textvar (name "FABRICATION_NOTES") "FABRICATION NOTES (UNLESS OTHERWISE SPECIFIED)\n\n1) FABRICATE PER IPC-6012A CLASS 2.\n\n2) OUTLINE DEFINED IN SEPARATE GERBER FILE WITH\n \"Edge_Cuts.GBR\" SUFFIX.\n\n3) SEE SEPARATE DRILL FILES WITH \".DRL\" SUFFIX \n FOR HOLE LOCATIONS.\n\n SELECTED HOLE LOCATIONS SHOWN ON THIS DRAWING \n FOR REFERENCE ONLY.\n\n4) SURFACE FINISH: ENIG\n\n5) SOLDERMASK ON BOTH SIDES OF THE BOARD SHALL \n BE LPI, COLOR GREEN.\n\n6) SILK SCREEN LEGEND TO BE APPLIED PER LAYER \n STACKUP USING WHITE NON-CONDUCTIVE EPOXY INK.\n\n7) ALL VIAS ARE TENTED ON BOTH SIDES UNLESS \n SOLDERMASK OPENED IN GERBER.\n\n8) RESERVED\n\n9) PCB MATERIAL REQUIREMENTS:\n\n A. FLAMMABILITY RATING MUST MEET OR EXCEED \n UL94V-0 REQUIREMENTS.\n B. Tg 135 C OR EQUIVALENT.\n\n10) DESIGN GEOMETRY MINIMUM FEATURE SIZES:\n\n BOARD SIZE N/A × N/A mm\n BOARD THICKNESS 1.647 mm\n TRACE WIDTH N/A mm\n TRACE TO TRACE 0.200 mm\n MIN. HOLE (PTH) N/A mm\n MIN. HOLE (NPTH) N/A mm\n ANNULAR RING N/A mm\n COPPER TO HOLE 0.250 mm\n COPPER TO EDGE 0.500 mm\n HOLE TO HOLE 0.250 mm\n\n11) ALL DIMENSIONS ARE IN MILLIMETERS UNLESS OTHERWISE\n SPECIFIED.\n\n12) FOR REFERENCE ONLY THE STACKUP CORRESPONDS TO JLCPCB\n STACKUP JLC04161H-7628.")
+ (textvar (name "GIT_HASH") "862bd3b")
+ (textvar (name "GIT_HASH_PCB") "862bd3b")
+ (textvar (name "GIT_HASH_SCH") "862bd3b")
+ (textvar (name "GIT_URL") "/jkrauss/Test_4")
+ (textvar (name "PROJECT_CODE") "P99")
+ (textvar (name "RELEASE_DATE") "2026-03-10")
+ (textvar (name "RELEASE_STATE") "DRAFT")
+ (textvar (name "REVISION") "NO_TAG+ (Unreleased)")
+ (textvar (name "SCALE") "1:1")
+ (textvar (name "SCHEMATIC_NOTES") "Unless otherwise specified, components Values are in ohms, µF, and µH.")
+ (textvar (name "SHEET_NAME_01") "Cover Page")
+ (textvar (name "SHEET_NAME_02") "Block Diagram")
+ (textvar (name "SHEET_NAME_03") "Project Architecture")
+ (textvar (name "SHEET_NAME_04") "Circuit 1")
+ (textvar (name "SHEET_NAME_05") "Circuit 2")
+ (textvar (name "SHEET_NAME_06") "Circuit 3")
+ (textvar (name "SHEET_NAME_07") "......................................")
+ (textvar (name "SHEET_NAME_08") "......................................")
+ (textvar (name "SHEET_NAME_09") "......................................")
+ (textvar (name "SHEET_NAME_10") "......................................")
+ (textvar (name "SHEET_NAME_11") "......................................")
+ (textvar (name "SHEET_NAME_12") "......................................")
+ (textvar (name "SHEET_NAME_13") "......................................")
+ (textvar (name "SHEET_NAME_14") "......................................")
+ (textvar (name "SHEET_NAME_15") "......................................")
+ (textvar (name "SHEET_NAME_16") "......................................")
+ (textvar (name "SHEET_NAME_17") "......................................")
+ (textvar (name "SHEET_NAME_18") "......................................")
+ (textvar (name "SHEET_NAME_19") "......................................")
+ (textvar (name "SHEET_NAME_20") "......................................")
+ (textvar (name "STATE") "TEMPLATE")
+ (textvar (name "VARIANT"))
+ (sheet (number "1") (name "/") (tstamps "/")
+ (title_block
+ (title "Title Page")
+ (company "Asymworks, LLC")
+ (rev "NO_TAG+ (Unreleased)")
+ (date)
+ (source "Asymworks_Template.kicad_sch")
+ (comment (number "1") (value ""))
+ (comment (number "2") (value ""))
+ (comment (number "3") (value ""))
+ (comment (number "4") (value ""))
+ (comment (number "5") (value ""))
+ (comment (number "6") (value ""))
+ (comment (number "7") (value ""))
+ (comment (number "8") (value ""))
+ (comment (number "9") (value ""))))
+ (sheet (number "2") (name "/Block Diagram/") (tstamps "/28ad8293-baaf-4ee1-8056-ad34096542a0/")
+ (title_block
+ (title "Block Diagram")
+ (company "Asymworks, LLC")
+ (rev "NO_TAG+ (Unreleased)")
+ (date)
+ (source "Block_Diagram.kicad_sch")
+ (comment (number "1") (value ""))
+ (comment (number "2") (value ""))
+ (comment (number "3") (value ""))
+ (comment (number "4") (value ""))
+ (comment (number "5") (value ""))
+ (comment (number "6") (value ""))
+ (comment (number "7") (value ""))
+ (comment (number "8") (value ""))
+ (comment (number "9") (value ""))))
+ (sheet (number "3") (name "/Project Architecture/") (tstamps "/f6afef58-d841-4ad6-baf9-746b0a35f011/")
+ (title_block
+ (title "Project Architecture")
+ (company "Asymworks, LLC")
+ (rev "NO_TAG+ (Unreleased)")
+ (date)
+ (source "Architecture.kicad_sch")
+ (comment (number "1") (value ""))
+ (comment (number "2") (value ""))
+ (comment (number "3") (value ""))
+ (comment (number "4") (value ""))
+ (comment (number "5") (value ""))
+ (comment (number "6") (value ""))
+ (comment (number "7") (value ""))
+ (comment (number "8") (value ""))
+ (comment (number "9") (value ""))))
+ (sheet (number "4") (name "/Project Architecture/Circuit 1/") (tstamps "/f6afef58-d841-4ad6-baf9-746b0a35f011/a5aa3c11-5084-4ea5-9da5-c9ff4a86f01f/")
+ (title_block
+ (title "Circuit 1")
+ (company "Asymworks, LLC")
+ (rev "NO_TAG+ (Unreleased)")
+ (date)
+ (source "Circuit-1.kicad_sch")
+ (comment (number "1") (value ""))
+ (comment (number "2") (value ""))
+ (comment (number "3") (value ""))
+ (comment (number "4") (value ""))
+ (comment (number "5") (value ""))
+ (comment (number "6") (value ""))
+ (comment (number "7") (value ""))
+ (comment (number "8") (value ""))
+ (comment (number "9") (value ""))))
+ (sheet (number "5") (name "/Project Architecture/Circuit 2/") (tstamps "/f6afef58-d841-4ad6-baf9-746b0a35f011/9da43fd7-7a0a-403c-bf2c-ba67cd8fa669/")
+ (title_block
+ (title "Circuit 2")
+ (company "Asymworks, LLC")
+ (rev "NO_TAG+ (Unreleased)")
+ (date)
+ (source "Circuit-2.kicad_sch")
+ (comment (number "1") (value ""))
+ (comment (number "2") (value ""))
+ (comment (number "3") (value ""))
+ (comment (number "4") (value ""))
+ (comment (number "5") (value ""))
+ (comment (number "6") (value ""))
+ (comment (number "7") (value ""))
+ (comment (number "8") (value ""))
+ (comment (number "9") (value ""))))
+ (sheet (number "6") (name "/Project Architecture/Circuit 3/") (tstamps "/f6afef58-d841-4ad6-baf9-746b0a35f011/6c8ce547-8e28-496a-9003-0e7dbfd93e8c/")
+ (title_block
+ (title)
+ (company "Asymworks, LLC")
+ (rev "NO_TAG+ (Unreleased)")
+ (date)
+ (source "Circuit-3.kicad_sch")
+ (comment (number "1") (value ""))
+ (comment (number "2") (value ""))
+ (comment (number "3") (value ""))
+ (comment (number "4") (value ""))
+ (comment (number "5") (value ""))
+ (comment (number "6") (value ""))
+ (comment (number "7") (value ""))
+ (comment (number "8") (value ""))
+ (comment (number "9") (value "")))))
+ (components)
+ (libparts)
+ (libraries)
+ (nets))
\ No newline at end of file
diff --git a/Asymworks_Template.kicad_pro b/Asymworks_Template.kicad_pro
index e17f5b5..97dca94 100644
--- a/Asymworks_Template.kicad_pro
+++ b/Asymworks_Template.kicad_pro
@@ -649,32 +649,35 @@
]
],
"text_variables": {
- "ASSEMBLY_NAME": "",
- "ASSEMBLY_NUMBER": "",
- "ASSEMBLY_SCALE": "",
+ "ASSEMBLY_NAME": "Assembly Name",
+ "ASSEMBLY_NOTES": "ASSEMBLY NOTES (UNLESS OTHERWISE SPECIFIED)\n\n1)\tDO NOT POPULATE COMPONENTS ARE MARKED WITH A RED CROSS\n\n2)\tDO NOT POPULATE COMPONENTS ARE NOT PRESENT IN THE BOM\n\n3)\tIF CONFLICTING INFORMATION IS FOUND BETWEEN THE ASSEMBLY\n\tFILE AND BOM, BOM SHOULD BE USED AS THE MAIN SOURCE.\n\n4)\tDOT IDENTIFIES PIN #1 LOCATION AND DEVICE ORIENTATION\n\tWHEN VIEWED FROM THE TOP.",
+ "ASSEMBLY_NUMBER": "A99-9000",
+ "ASSEMBLY_SCALE": "1",
"COMPANY": "Asymworks, LLC",
"DESIGNER": "JPK",
- "DWG_NUMBER_PCB": "",
- "DWG_NUMBER_SCH": "",
- "DWG_TITLE_ASSY": "",
- "DWG_TITLE_PCB": "",
- "DWG_TITLE_SCH": "",
- "GIT_HASH": "",
- "GIT_HASH_PCB": "",
- "GIT_HASH_SCH": "",
- "GIT_URL": "",
- "PROJECT_CODE": "",
- "RELEASE_DATE": "",
- "RELEASE_STATE": "",
- "REVISION": "${REVISION}",
+ "DWG_NUMBER_PCB": "P99-9000",
+ "DWG_NUMBER_SCH": "S99-9000",
+ "DWG_TITLE_ASSY": "PCB Assembly, Assembly Name",
+ "DWG_TITLE_PCB": "PCB, Assembly Name",
+ "DWG_TITLE_SCH": "Schematic, Assembly Name",
+ "FABRICATION_NOTES": "FABRICATION NOTES (UNLESS OTHERWISE SPECIFIED)\n\n1)\tFABRICATE PER IPC-6012A CLASS 2.\n\n2)\tOUTLINE DEFINED IN SEPARATE GERBER FILE WITH\n\t\"Edge_Cuts.GBR\" SUFFIX.\n\n3)\tSEE SEPARATE DRILL FILES WITH \".DRL\" SUFFIX \n\tFOR HOLE LOCATIONS.\n\n\tSELECTED HOLE LOCATIONS SHOWN ON THIS DRAWING \n\tFOR REFERENCE ONLY.\n\n4)\tSURFACE FINISH: ENIG\n\n5)\tSOLDERMASK ON BOTH SIDES OF THE BOARD SHALL \n\tBE LPI, COLOR GREEN.\n\n6)\tSILK SCREEN LEGEND TO BE APPLIED PER LAYER \n\tSTACKUP USING WHITE NON-CONDUCTIVE EPOXY INK.\n\n7)\tALL VIAS ARE TENTED ON BOTH SIDES UNLESS \n\tSOLDERMASK OPENED IN GERBER.\n\n8)\tRESERVED\n\n9)\tPCB MATERIAL REQUIREMENTS:\n\n\tA.\tFLAMMABILITY RATING MUST MEET OR EXCEED \n\t\tUL94V-0 REQUIREMENTS.\n\tB.\tTg 135 C OR EQUIVALENT.\n\n10)\tDESIGN GEOMETRY MINIMUM FEATURE SIZES:\n\n\tBOARD SIZE\t\t\t\tN/A \u00d7 N/A mm\n\tBOARD THICKNESS\t\t1.647 mm\n\tTRACE WIDTH\t\t\tN/A mm\n\tTRACE TO TRACE\t\t0.200 mm\n\tMIN. HOLE (PTH)\t\t\tN/A mm\n\tMIN. HOLE (NPTH)\t\tN/A mm\n\tANNULAR RING\t\t\tN/A mm\n\tCOPPER TO HOLE\t\t0.250 mm\n\tCOPPER TO EDGE\t\t0.500 mm\n\tHOLE TO HOLE\t\t\t0.250 mm\n\n11)\tALL DIMENSIONS ARE IN MILLIMETERS UNLESS OTHERWISE\n\tSPECIFIED.\n\n12)\tFOR REFERENCE ONLY THE STACKUP CORRESPONDS TO JLCPCB\n\tSTACKUP JLC04161H-7628.",
+ "GIT_HASH": "862bd3b",
+ "GIT_HASH_PCB": "862bd3b",
+ "GIT_HASH_SCH": "862bd3b",
+ "GIT_URL": "/jkrauss/Test_4",
+ "PROJECT_CODE": "P99",
+ "RELEASE_DATE": "2026-03-10",
+ "RELEASE_STATE": "DRAFT",
+ "REVISION": "NO_TAG+ (Unreleased)",
"SCALE": "1:1",
+ "SCHEMATIC_NOTES": "Unless otherwise specified, components Values are in ohms, \u00b5F, and \u00b5H.",
"SHEET_NAME_01": "Cover Page",
"SHEET_NAME_02": "Block Diagram",
"SHEET_NAME_03": "Project Architecture",
"SHEET_NAME_04": "Circuit 1",
"SHEET_NAME_05": "Circuit 2",
"SHEET_NAME_06": "Circuit 3",
- "SHEET_NAME_07": "Parts List",
+ "SHEET_NAME_07": "......................................",
"SHEET_NAME_08": "......................................",
"SHEET_NAME_09": "......................................",
"SHEET_NAME_10": "......................................",
@@ -691,4 +694,4 @@
"STATE": "TEMPLATE",
"VARIANT": ""
}
-}
+}
\ No newline at end of file
diff --git a/Asymworks_Template.xml b/Asymworks_Template.xml
new file mode 100644
index 0000000..432dac3
--- /dev/null
+++ b/Asymworks_Template.xml
@@ -0,0 +1,223 @@
+
+
+
+ /workspace/jkrauss/Test_7/Asymworks_Template.kicad_sch
+ Date1
+ Eeschema 9.0.7+1
+ Assembly Name
+ ASSEMBLY NOTES (UNLESS OTHERWISE SPECIFIED)
+
+1) DO NOT POPULATE COMPONENTS ARE MARKED WITH A RED CROSS
+
+2) DO NOT POPULATE COMPONENTS ARE NOT PRESENT IN THE BOM
+
+3) IF CONFLICTING INFORMATION IS FOUND BETWEEN THE ASSEMBLY
+ FILE AND BOM, BOM SHOULD BE USED AS THE MAIN SOURCE.
+
+4) DOT IDENTIFIES PIN #1 LOCATION AND DEVICE ORIENTATION
+ WHEN VIEWED FROM THE TOP.
+ A99-9000
+ 1
+ Asymworks, LLC
+ JPK
+ P99-9000
+ S99-9000
+ PCB Assembly, Assembly Name
+ PCB, Assembly Name
+ Schematic, Assembly Name
+ FABRICATION NOTES (UNLESS OTHERWISE SPECIFIED)
+
+1) FABRICATE PER IPC-6012A CLASS 2.
+
+2) OUTLINE DEFINED IN SEPARATE GERBER FILE WITH
+ "Edge_Cuts.GBR" SUFFIX.
+
+3) SEE SEPARATE DRILL FILES WITH ".DRL" SUFFIX
+ FOR HOLE LOCATIONS.
+
+ SELECTED HOLE LOCATIONS SHOWN ON THIS DRAWING
+ FOR REFERENCE ONLY.
+
+4) SURFACE FINISH: ENIG
+
+5) SOLDERMASK ON BOTH SIDES OF THE BOARD SHALL
+ BE LPI, COLOR GREEN.
+
+6) SILK SCREEN LEGEND TO BE APPLIED PER LAYER
+ STACKUP USING WHITE NON-CONDUCTIVE EPOXY INK.
+
+7) ALL VIAS ARE TENTED ON BOTH SIDES UNLESS
+ SOLDERMASK OPENED IN GERBER.
+
+8) RESERVED
+
+9) PCB MATERIAL REQUIREMENTS:
+
+ A. FLAMMABILITY RATING MUST MEET OR EXCEED
+ UL94V-0 REQUIREMENTS.
+ B. Tg 135 C OR EQUIVALENT.
+
+10) DESIGN GEOMETRY MINIMUM FEATURE SIZES:
+
+ BOARD SIZE N/A × N/A mm
+ BOARD THICKNESS 1.647 mm
+ TRACE WIDTH N/A mm
+ TRACE TO TRACE 0.200 mm
+ MIN. HOLE (PTH) N/A mm
+ MIN. HOLE (NPTH) N/A mm
+ ANNULAR RING N/A mm
+ COPPER TO HOLE 0.250 mm
+ COPPER TO EDGE 0.500 mm
+ HOLE TO HOLE 0.250 mm
+
+11) ALL DIMENSIONS ARE IN MILLIMETERS UNLESS OTHERWISE
+ SPECIFIED.
+
+12) FOR REFERENCE ONLY THE STACKUP CORRESPONDS TO JLCPCB
+ STACKUP JLC04161H-7628.
+ 862bd3b
+ 862bd3b
+ 862bd3b
+ /jkrauss/Test_4
+ P99
+ 2026-03-10
+ DRAFT
+ NO_TAG+ (Unreleased)
+ 1:1
+ Unless otherwise specified, components Values are in ohms, µF, and µH.
+ Cover Page
+ Block Diagram
+ Project Architecture
+ Circuit 1
+ Circuit 2
+ Circuit 3
+ ......................................
+ ......................................
+ ......................................
+ ......................................
+ ......................................
+ ......................................
+ ......................................
+ ......................................
+ ......................................
+ ......................................
+ ......................................
+ ......................................
+ ......................................
+ ......................................
+ TEMPLATE
+
+
+
+ Title Page
+ Asymworks, LLC
+ NO_TAG+ (Unreleased)
+
+ Asymworks_Template.kicad_sch
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Block Diagram
+ Asymworks, LLC
+ NO_TAG+ (Unreleased)
+
+ Block_Diagram.kicad_sch
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Project Architecture
+ Asymworks, LLC
+ NO_TAG+ (Unreleased)
+
+ Architecture.kicad_sch
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Circuit 1
+ Asymworks, LLC
+ NO_TAG+ (Unreleased)
+
+ Circuit-1.kicad_sch
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Circuit 2
+ Asymworks, LLC
+ NO_TAG+ (Unreleased)
+
+ Circuit-2.kicad_sch
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Asymworks, LLC
+ NO_TAG+ (Unreleased)
+
+ Circuit-3.kicad_sch
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/mfg/assembly/Asymworks_Template-assembly_notes.txt b/mfg/assembly/Asymworks_Template-assembly_notes.txt
new file mode 100644
index 0000000..506d09e
--- /dev/null
+++ b/mfg/assembly/Asymworks_Template-assembly_notes.txt
@@ -0,0 +1,11 @@
+ASSEMBLY NOTES (UNLESS OTHERWISE SPECIFIED)
+
+1) DO NOT POPULATE COMPONENTS ARE MARKED WITH A RED CROSS
+
+2) DO NOT POPULATE COMPONENTS ARE NOT PRESENT IN THE BOM
+
+3) IF CONFLICTING INFORMATION IS FOUND BETWEEN THE ASSEMBLY
+ FILE AND BOM, BOM SHOULD BE USED AS THE MAIN SOURCE.
+
+4) DOT IDENTIFIES PIN #1 LOCATION AND DEVICE ORIENTATION
+ WHEN VIEWED FROM THE TOP.
diff --git a/mfg/assembly/Asymworks_Template-bom.csv b/mfg/assembly/Asymworks_Template-bom.csv
new file mode 100644
index 0000000..f5b03aa
--- /dev/null
+++ b/mfg/assembly/Asymworks_Template-bom.csv
@@ -0,0 +1 @@
+Row,Quantity Per PCB,References,Value,Datasheet,Footprint,Description,Asymworks IPN,Manufacturer,Manufacturer PN,LCSC
diff --git a/mfg/assembly/Asymworks_Template-bom.html b/mfg/assembly/Asymworks_Template-bom.html
new file mode 100644
index 0000000..abaa6a7
--- /dev/null
+++ b/mfg/assembly/Asymworks_Template-bom.html
@@ -0,0 +1,242 @@
+
+
+
+ Bill of Materials
+
+
+
+
+
+
+
+
+ Bill of Materials
+
+
+
+
+ Schematic : Asymworks_Template
+ Variant : default
+ Revision : NO_TAG+ (Unreleased)
+ Date : 2026-03-10_23-05-42
+ KiCad Version : 9.0.7+1
+
+
+ Component Groups : 0
+ Component Count : 0 (per PCB)
+
+ Fitted Components : 0 (per PCB)
+ Number of PCBs : 1
+ Total Components : 0 (for 1 PCBs)
+
+
+
+Component Groups
+
+
+
+ Row
+ Quantity Per PCB
+ References
+ Value
+ Datasheet
+ Footprint
+ Description
+ Asymworks IPN
+ Manufacturer
+ Manufacturer PN
+ LCSC
+
+
+
+
+
+
+Color reference for columns:
+KiCad Fields (default)
+Generated Fields
+User Fields
+Empty Fields
+
+
+
\ No newline at end of file
diff --git a/mfg/assembly/Asymworks_Template-components_count.csv b/mfg/assembly/Asymworks_Template-components_count.csv
new file mode 100644
index 0000000..2a7f64c
--- /dev/null
+++ b/mfg/assembly/Asymworks_Template-components_count.csv
@@ -0,0 +1,4 @@
+Type,Front Side,Back Side,Total
+THT,0,0,0
+SMD,0,0,0
+Total,0,0,0
diff --git a/mfg/fab/Asymworks_Template-fabrication_notes.txt b/mfg/fab/Asymworks_Template-fabrication_notes.txt
new file mode 100644
index 0000000..399ef3f
--- /dev/null
+++ b/mfg/fab/Asymworks_Template-fabrication_notes.txt
@@ -0,0 +1,50 @@
+FABRICATION NOTES (UNLESS OTHERWISE SPECIFIED)
+
+1) FABRICATE PER IPC-6012A CLASS 2.
+
+2) OUTLINE DEFINED IN SEPARATE GERBER FILE WITH
+ "Edge_Cuts.GBR" SUFFIX.
+
+3) SEE SEPARATE DRILL FILES WITH ".DRL" SUFFIX
+ FOR HOLE LOCATIONS.
+
+ SELECTED HOLE LOCATIONS SHOWN ON THIS DRAWING
+ FOR REFERENCE ONLY.
+
+4) SURFACE FINISH: ENIG
+
+5) SOLDERMASK ON BOTH SIDES OF THE BOARD SHALL
+ BE LPI, COLOR GREEN.
+
+6) SILK SCREEN LEGEND TO BE APPLIED PER LAYER
+ STACKUP USING WHITE NON-CONDUCTIVE EPOXY INK.
+
+7) ALL VIAS ARE TENTED ON BOTH SIDES UNLESS
+ SOLDERMASK OPENED IN GERBER.
+
+8) RESERVED
+
+9) PCB MATERIAL REQUIREMENTS:
+
+ A. FLAMMABILITY RATING MUST MEET OR EXCEED
+ UL94V-0 REQUIREMENTS.
+ B. Tg 135 C OR EQUIVALENT.
+
+10) DESIGN GEOMETRY MINIMUM FEATURE SIZES:
+
+ BOARD SIZE N/A × N/A mm
+ BOARD THICKNESS 1.647 mm
+ TRACE WIDTH N/A mm
+ TRACE TO TRACE 0.200 mm
+ MIN. HOLE (PTH) N/A mm
+ MIN. HOLE (NPTH) N/A mm
+ ANNULAR RING N/A mm
+ COPPER TO HOLE 0.250 mm
+ COPPER TO EDGE 0.500 mm
+ HOLE TO HOLE 0.250 mm
+
+11) ALL DIMENSIONS ARE IN MILLIMETERS UNLESS OTHERWISE
+ SPECIFIED.
+
+12) FOR REFERENCE ONLY THE STACKUP CORRESPONDS TO JLCPCB
+ STACKUP JLC04161H-7628.
diff --git a/mfg/fab/Asymworks_Template-impedance_table.csv b/mfg/fab/Asymworks_Template-impedance_table.csv
new file mode 100644
index 0000000..328be7f
--- /dev/null
+++ b/mfg/fab/Asymworks_Template-impedance_table.csv
@@ -0,0 +1,4 @@
+Layer,Ref1,Ref2,Type,Impedance,Width,Space,Tolerance
+L1,AIR,L2,SE,50,0.349,-----,10%
+L1,AIR,L2,DIFF,90,0.286,0.203,10%
+L1,AIR,L2,DIFF,100,0.221,0.203,10%
\ No newline at end of file
diff --git a/schematic/Asymworks_Template-schematic.pdf b/schematic/Asymworks_Template-schematic.pdf
new file mode 100644
index 0000000..7ec840f
Binary files /dev/null and b/schematic/Asymworks_Template-schematic.pdf differ
diff --git a/schematic/Asymworks_Template-schematic_notes.txt b/schematic/Asymworks_Template-schematic_notes.txt
new file mode 100644
index 0000000..4e0eac3
--- /dev/null
+++ b/schematic/Asymworks_Template-schematic_notes.txt
@@ -0,0 +1 @@
+Unless otherwise specified, components Values are in ohms, µF, and µH.
\ No newline at end of file
diff --git a/test/testpoints/Asymworks_Template-testpoints-bottom.csv b/test/testpoints/Asymworks_Template-testpoints-bottom.csv
new file mode 100644
index 0000000..72e7939
--- /dev/null
+++ b/test/testpoints/Asymworks_Template-testpoints-bottom.csv
@@ -0,0 +1 @@
+Ref.,Net,X [mm],Y [mm]
diff --git a/test/testpoints/Asymworks_Template-testpoints-top.csv b/test/testpoints/Asymworks_Template-testpoints-top.csv
new file mode 100644
index 0000000..72e7939
--- /dev/null
+++ b/test/testpoints/Asymworks_Template-testpoints-top.csv
@@ -0,0 +1 @@
+Ref.,Net,X [mm],Y [mm]
diff --git a/test/testpoints/Asymworks_Template-testpoints.csv b/test/testpoints/Asymworks_Template-testpoints.csv
new file mode 100644
index 0000000..6daa3d6
--- /dev/null
+++ b/test/testpoints/Asymworks_Template-testpoints.csv
@@ -0,0 +1 @@
+Testpoint Ref.,Net,Net Class,X,Y,Side,Pad Type,Value,Footprint