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jkrauss
2026-03-06 17:00:16 +00:00
committed by github-actions[bot]
parent 0e4308be37
commit b752ffdc56
4 changed files with 2151 additions and 2 deletions
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2
Test_5-netlist.net
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@@ -15,7 +15,7 @@
(textvar (name "DWG_TITLE_PCB") "PCB, Assembly Name")
(textvar (name "DWG_TITLE_SCH") "Schematic, Assembly Name")
(textvar (name "FABRICATION_NOTES") "FABRICATION NOTES (UNLESS OTHERWISE SPECIFIED)\n\n1) FABRICATE PER IPC-6012A CLASS 2.\n\n2) OUTLINE DEFINED IN SEPARATE GERBER FILE WITH\n \"Edge_Cuts.GBR\" SUFFIX.\n\n3) SEE SEPARATE DRILL FILES WITH \".DRL\" SUFFIX \n FOR HOLE LOCATIONS.\n\n SELECTED HOLE LOCATIONS SHOWN ON THIS DRAWING \n FOR REFERENCE ONLY.\n\n4) SURFACE FINISH: HAL SNPB\n\n5) SOLDERMASK ON BOTH SIDES OF THE BOARD SHALL \n BE LPI, COLOR GREEN.\n\n6) SILK SCREEN LEGEND TO BE APPLIED PER LAYER \n STACKUP USING WHITE NON-CONDUCTIVE EPOXY INK.\n\n7) ALL VIAS ARE TENTED ON BOTH SIDES UNLESS \n SOLDERMASK OPENED IN GERBER.\n\n8) RESERVED\n\n9) PCB MATERIAL REQUIREMENTS:\n\n A. FLAMMABILITY RATING MUST MEET OR EXCEED \n UL94V-0 REQUIREMENTS.\n B. Tg 135 C OR EQUIVALENT.\n\n10) DESIGN GEOMETRY MINIMUM FEATURE SIZES:\n\n BOARD SIZE 46.000 × 27.500 mm\n BOARD THICKNESS 1.647 mm\n TRACE WIDTH 0.100 mm\n TRACE TO TRACE 0.200 mm\n MIN. HOLE (PTH) 0.300 mm\n MIN. HOLE (NPTH) 2.200 mm\n ANNULAR RING 0.150 mm\n COPPER TO HOLE 0.250 mm\n COPPER TO EDGE 0.500 mm\n HOLE TO HOLE 0.250 mm\n\n11) ALL DIMENSIONS ARE IN MILLIMETERS UNLESS OTHERWISE\n SPECIFIED.")
(textvar (name "GIT_HASH") "02b8af5")
(textvar (name "GIT_HASH") "0e4308b")
(textvar (name "GIT_HASH_PCB") "1fa3de1")
(textvar (name "GIT_HASH_SCH") "02b8af5")
(textvar (name "GIT_URL") "/jkrauss/Test_4")

2
Test_5.kicad_pro
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@@ -846,7 +846,7 @@
"DWG_TITLE_PCB": "PCB, Assembly Name",
"DWG_TITLE_SCH": "Schematic, Assembly Name",
"FABRICATION_NOTES": "FABRICATION NOTES (UNLESS OTHERWISE SPECIFIED)\n\n1)\tFABRICATE PER IPC-6012A CLASS 2.\n\n2)\tOUTLINE DEFINED IN SEPARATE GERBER FILE WITH\n\t\"Edge_Cuts.GBR\" SUFFIX.\n\n3)\tSEE SEPARATE DRILL FILES WITH \".DRL\" SUFFIX \n\tFOR HOLE LOCATIONS.\n\n\tSELECTED HOLE LOCATIONS SHOWN ON THIS DRAWING \n\tFOR REFERENCE ONLY.\n\n4)\tSURFACE FINISH: HAL SNPB\n\n5)\tSOLDERMASK ON BOTH SIDES OF THE BOARD SHALL \n\tBE LPI, COLOR GREEN.\n\n6)\tSILK SCREEN LEGEND TO BE APPLIED PER LAYER \n\tSTACKUP USING WHITE NON-CONDUCTIVE EPOXY INK.\n\n7)\tALL VIAS ARE TENTED ON BOTH SIDES UNLESS \n\tSOLDERMASK OPENED IN GERBER.\n\n8)\tRESERVED\n\n9)\tPCB MATERIAL REQUIREMENTS:\n\n\tA.\tFLAMMABILITY RATING MUST MEET OR EXCEED \n\t\tUL94V-0 REQUIREMENTS.\n\tB.\tTg 135 C OR EQUIVALENT.\n\n10)\tDESIGN GEOMETRY MINIMUM FEATURE SIZES:\n\n\tBOARD SIZE\t\t\t\t46.000 \u00d7 27.500 mm\n\tBOARD THICKNESS\t\t1.647 mm\n\tTRACE WIDTH\t\t\t0.100 mm\n\tTRACE TO TRACE\t\t0.200 mm\n\tMIN. HOLE (PTH)\t\t\t0.300 mm\n\tMIN. HOLE (NPTH)\t\t2.200 mm\n\tANNULAR RING\t\t\t0.150 mm\n\tCOPPER TO HOLE\t\t0.250 mm\n\tCOPPER TO EDGE\t\t0.500 mm\n\tHOLE TO HOLE\t\t\t0.250 mm\n\n11)\tALL DIMENSIONS ARE IN MILLIMETERS UNLESS OTHERWISE\n\tSPECIFIED.",
"GIT_HASH": "02b8af5",
"GIT_HASH": "0e4308b",
"GIT_HASH_PCB": "1fa3de1",
"GIT_HASH_SCH": "02b8af5",
"GIT_URL": "/jkrauss/Test_4",

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Test_5.xml Normal file
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schematic/Test_5-schematic.pdf
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